Phase-locked loops (PLLs) are widely used in electronic circuits to generate signals with closely controlled timing relationships. A few of the wide range of PLL applications include integral and fractional clock signal multiplication, clock signal recovery from a data bitstream, clock signal and data re-timing and de-skewing, and clock signal synthesis. Generally, the PLL is an indispensable building block in the design of any analog or mixed-signal circuits in which a precise timing relationship must be established between two signals.
A number of different PLL designs are known in the art. In one particular design, a phase-frequency detector determines the deviation (error) from a desired timing relationship between the edges of a voltage controlled oscillator (VCO) generated signal and a reference signal. A charge pump generates a current proportional to the detected error, which is then integrated in a loop-filter to generate a control voltage controlling the output frequency of the VCO. The output frequency of the VCO is divided by a desired divisor and fed-back to the phase frequency detector for comparison against the reference signal and thereby close the loop. As the error changes, the control voltage varies the output frequency of the VCO such that the desired timing relationship between the edges of the VCO generated signal and those of the reference signal is maintained. Therefore, the output signal from the VCO ideally has a precise timing relationship with the reference signal.
One very important PLL design consideration is jitter, which generally is defined as the error in significant timing instances, such as the edges of the VCO output signal and/or the edges of the reference signal, from their ideal positions. One specific source of jitter is the charge pump, in PLLs using a charge-pump. For example, the charge pump may introduce a fixed offset charge into the loop filter, resulting in a deviation of the VCO control voltage from its ideal value. Compensation is possible by introducing a static timing skew between the reference and VCO generated signals and/or by introducing a charge of opposite polarity at the charge pump output. However, the compensation scheme may, in itself, introduce voltage ripples and mismatch thereby introducing dynamic jitter and skew into the system.
Glitching is another consideration. Voltage switching charge pumps generally pass bias currents through metal oxide semiconductor field effect transistor (MOSFET) switches biased in the triode region when in the “on” state. This technique, however, requires that the MOSFETs be driven by rail to rail logic signals at their gates, which causes large step voltages to couple across the gate to drain capacitances and consequently unacceptable glitching currents or charges. Glitching also occurs in voltage switching charge pumps due to inverter and gate delay mismatches and charge-sharing.
On the other hand, some current switching charge pumps utilize differential MOSFET pairs to switch bias currents into and out of an output node. This technique requires that both high and low levels be generated for controlling the gates of the differential pair. These levels are generated, for example, with two diode-connected MOSFETs biased in strong inversion at two different current densities. However, the output node must be driven with a low output impedance. As a result, large MOSFETs are required in the differential pair, as well as large bias currents. Additionally, the common mode voltage must be adjusted to ensure that the tail-current biasing transistor associated with the differential pair is maintained in the saturation region. Consequently, the entire circuit structure is highly sensitive to process corners (i.e. process-voltage-temperature or PVT).
In sum, new PLL techniques are required which minimize the amount of skew and jitter in the PLL output signal. Furthermore, output glitches should be substantially reduced without the need for large switching transistors or significant additional circuitry. These techniques should be particularly applicable to charge pump-based PLL circuits and the wide range of systems utilizing such circuits.